The present invention relates to synchronization of serial digital audio signals, and more particularly to a simple digital audio frame and block synchronization using a 50% duty cycle reference signal with a different duty cycle every Nth cycle corresponding to the block span.
An internationally known standard for the interchange of digital audio is AES3-1992. Under this standard two channels of audio are digitized and then time multiplexed into a single serial digital data stream. This data stream contains certain synchronizing symbols, or preambles, that are used by a receiver of the data stream to demultiplex and deserialize the two digital audio channels. In addition to the digitized audio samples, each sample within the data stream also contains auxiliary information in the form of a channel status bit, a user data bit, a validity bit and a parity bit. The validity and parity bits pertain only to the samples in which they are contained, but the channel status and user data bits form blocks of data that span 192 samples. A special preamble in the AES data stream indicates the start of a new 192 sample block.
When it is desirable to synchronize multiple systems, or multiple channels within a system, a reference clock with 50% duty cycle, such as a 48 KHz clock typical for AES, may be distributed. Phase-locked loops (PLLs) in a system may then be connected directly to this clock, as shown in FIG. 1. An oscillator generates a master clock and from the master clock other audio clocks that are multiples of the reference clock. The problem is that no block alignment is made between systems, only frame alignment.
To maintain block alignment an AES signal may be used as the system reference, as shown in FIG. 2. The problem with this approach is that it takes more circuitry and complexity to derive a reference clock from the AES reference signal.
Another possible solution to this problem is to distribute a block reference clock, as shown in FIG. 3. The problem with this approach is that, due to the relatively low frequency of the block reference clock, it is difficult to get a PLL to lock in a brief time period, which eliminates this as a reasonable solution.
What is desired is a simple solution for providing both frame and block synchronization for digital audio signals.